1. Field of the Invention
The present invention generally relates to divide-by-N circuits for dividing the frequency of a master clock signal in order to obtain a clock signal having a different frequency from that of the master clock signal. The present invention more particularly relates to a high-speed programmable divider capable of providing an output clock signal having an increased duty cycle and a programmable delay chain.
2. Background Art
Divider circuits are well-known circuits that are used to divide the frequency of a clock signal (e.g., a system clock) by a specific number of counts. That is, for N clock pulses input into the circuit, only one output pulse is generated.
These divider circuits are used for a number of different applications. In particular, divider circuits are used to reduce the overall number of oscillators required on a given semiconductor chip, thereby making available additional room on the chip to place as much other circuitry as possible. Variable control oscillators (VCOs), for example, are commonly used in phase lock loop (PLL) circuits. Often, a single VCO circuit is provided that generates a master clock signal. One or more divider circuits may then be used to generate clock signals having different frequencies.
Typically, one or more divide-by-2 circuits are used to divide the master clock signal frequency by a factor of 2, 4, 8, etc. More particularly, most conventional divider circuits divide the master clock signal frequency by a divide ratio that is a power of 2. These conventional divider circuits normally comprise a number of D flip flops, which may be configured for use in a divider circuit by tying the Q bar to D. One D flip flop configured in this manner equates to divide by 2. Two flip flops equates to divide by 4, and three flip flops equates to divide by 8, and so on.
On the other hand, other types of divider circuits maybe easily configured to accommodate any single divide ratio, regardless of whether the particular ratio is a power of 2 or not. The Johnson counter is one such device and may be configured to accommodate any divide ratio (e.g., 2, 3, 4, 5, or 6). For this reasons, Johnson counters are often among the most commonly used counters in divider circuits.
One problem with divider circuits using conventional counters, such as the Johnson counter, is that each circuit must be configured in accordance with only one divide ratio. That is, a particular divider circuit may only be configured to accommodate a divide ratio of 2, 3, or 4, etc., and not 2, 3, and 4. Further, although the Johnson counter is desirably because of its ability to accommodate any single divide ratio, it produces signal having undesirable duty cycles. For example, most modern PLLs, as well as other high-speed application, require clock signals having duty cycles on the order of about 50%. Typical Johnson counters, however, produce signals having much higher duty cycles.
What is needed, therefore, is a divider circuit reconfigurable to accommodate a variety of different frequency divide ratios. In addition, it would be desirable to have such a divider circuit that produces an output signal having a duty cycle suitable for high-speed applications, preferably on the order of about 50%. Further still, it would be desirable to have a divider circuit capable of selectively delaying the output clock signal to resolve timing issues.